Channel_number: 0.
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00500
usb1 0xFFB40000 0xFFB40500

Offset: 0x500

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


RO 0x0


RO 0x0



RW 0x0


RW 0x0


RW 0x0


RW 0x0


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


RW 0x0


RW 0x0


RW 0x0

hcchar0 Fields

Bit Name Description Access Reset
31 chena

When Scatter/Gather mode is disabled. This field is set by the application and cleared by the OTG host.

Value Description
0x0 Indicates that the descriptor structure is not yet ready
0x1 Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor
RO 0x0
30 chdis

The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel Disabled interrupt before treating the channel as disabled.

Value Description
0x0 No activity
0x1 Stop transmitting/receiving data
RO 0x0
28:22 devaddr

This field selects the specific device serving as the data source or sink.

RW 0x0
21:20 ec

When the Split Enable bit of the Host Channel-n Split Control register (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of transactions that must be executed per microframe for this periodic endpoint. for non periodic transfers, this field is used only in DMA mode, and specifies the number packets to be fetched for this channel before the internal DMA engine changes arbitration. When HCSPLTn.SpltEna is Set (1'b1), this field indicates the number of immediate retries to be performed for a periodic split transactions on transaction errors. This field must be Set to at least 2'b01.

Value Description
0x0 Reserved This field yields undefined results
0x1 1 transaction
0x2 2 transactions to be issued for this endpoint per microframe
0x3 3 transactions to be issued for this endpoint per microframe
RW 0x0
19:18 eptype

Indicates the transfer type selected.

Value Description
0x0 Control
0x1 Isochronous
0x2 Bulk
0x3 Interrupt
RW 0x0
17 lspddev

This field is Set by the application to indicate that this channel is communicating to a low-speed device. The application must program this bit when a low speed device is connected to the host through an FS HUB. The HS OTG Host core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host core ignores this bit even if it is set by the application software.

Value Description
0x0 Communicating with non lowspeed
0x1 Communicating with lowspeed
RW 0x0
15 epdir

Indicates whether the transaction is IN or OUT.

Value Description
0x0 OUT
0x1 IN
RW 0x0
14:11 epnum

Indicates the endpoint number on the device serving as the data source or sink.

Value Description
0x0 End point 0
0x1 End point 1
0x2 End point 2
0x3 End point 3
0x4 End point 4
0x5 End point 5
0x6 End point 6
0x7 End point 7
0x8 End point 8
0x9 End point 9
0xa End point 10
0xb End point 11
0xc End point 12
0xd End point 13
0xe End point 14
0xf End point 15
RW 0x0
10:0 mps

Indicates the maximum packet size of the associated endpoint.

RW 0x0