The SGMII/RGMII/SMII Status register indicates the status signals received by the RGMII interface (selected at reset) from the PHY.
Module Instance Base Address Register Address
emac0 0xFF700000 0xFF7000D8
emac1 0xFF702000 0xFF7020D8

Offset: 0xD8

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RO 0x0


RO 0x0


RO 0x0

SGMII_RGMII_SMII_Control_Status Fields

Bit Name Description Access Reset
3 lnksts

This bit indicates whether the link is up (1'b1) or down (1'b0).

Value Description
0x0 Linkdown
0x1 Linkup
RO 0x0
2:1 lnkspeed

This bit indicates the current speed of the link. Bit 2 is reserved when the MAC is configured for the SMII PHY interface.

Value Description
0x0 Link Speed 2.5MHz
0x1 Link Speed 25MHz
0x2 Link Speed 125MHz
RO 0x0
0 lnkmod

This bit indicates the current mode of operation of the link

Value Description
0x0 Half Duplex
0x1 Full Duplex
RO 0x0