Flow_Control

The Flow Control register controls the generation and reception of the Control (Pause Command) frames by the MAC's Flow control block. A Write to a register with the Busy bit set to '1' triggers the Flow Control block to generate a Pause Control frame. The fields of the control frame are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control frame. The Busy bit remains set until the control frame is transferred onto the cable. The Host must make sure that the Busy bit is cleared before writing to the register.
Module Instance Base Address Register Address
emac0 0xFF700000 0xFF700018
emac1 0xFF702000 0xFF702018

Offset: 0x18

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

pt

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

dzpq

RW 0x0

Reserved

plt

RW 0x0

up

RW 0x0

rfe

RW 0x0

tfe

RW 0x0

fca_bpa

RW 0x0

Flow_Control Fields

Bit Name Description Access Reset
31:16 pt

This field holds the value to be used in the Pause Time field in the transmit control frame. Because the Pause Time bits are double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain.

RW 0x0
7 dzpq

When this bit is set, it disables the automatic generation of the Zero-Quanta Pause Control frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled.

Value Description
0x1 Disable Auto Gen. of Zero-Quanta Pause
0x0 Enable Auto Gen. of Zero-Quanta Pause
RW 0x0
5:4 plt

This field configures the threshold of the PAUSE timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 - 28) slot times after the first PAUSE frame is transmitted. The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface.

Value Description
0x0 Pause time - 4 slot times
0x1 Pause time - 28 slot times
0x2 Pause time - 144 slot times
0x3 Pause time - 256 slot times
RW 0x0
3 up

When this bit is set, then in addition to the detecting Pause frames with the unique multicast address, the MAC detects the Pause frames with the station's unicast address specified in the MAC Address0 High Register and MAC Address0 Low Register. When this bit is reset, the MAC detects only a Pause frame with the unique multicast address specified in the 802.3x standard.

Value Description
0x0 MAC Detects Pause MCA
0x1 MAC Detects Pause MCA and UCA
RW 0x0
2 rfe

When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled.

Value Description
0x0 Decode Func. of Pause Frame Disabled
0x1 MAC decodes the received Pause
RW 0x0
1 tfe

In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. In half-duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the back-pressure feature is disabled.

Value Description
0x0 Transmit Flow Control Disable
0x1 Transmit Flow Control Enable
RW 0x0
0 fca_bpa

This bit initiates a Pause Control frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled.

Value Description
0x0 Pause Ctrl Frame and BPA off
0x1 Init Pause Ctrl Frame and BPA
RW 0x0