The GMII Address register controls the management cycles to the external PHY through the management interface.
Module Instance Base Address Register Address
emac0 0xFF700000 0xFF700010
emac1 0xFF702000 0xFF702010

Offset: 0x10

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


RW 0x0


RW 0x0


RW 0x0


RW 0x0


RW 0x0

GMII_Address Fields

Bit Name Description Access Reset
15:11 pa

This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII block.

RW 0x0
10:6 gr

These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set.

RW 0x0
5:2 cr

The CSR Clock Range selection determines the frequency of the MDC clock according to the l4_mp_clk frequency used in your design. The suggested range of l4_mp_clk frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. When Bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when l4_mp_clk is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Only use the values larger than 7 if the interfacing chips support faster MDC clocks.

Value Description
0x0 l4_mp_clk 60-100Mhz and MDC clock = l4_mp_clk/42
0x1 l4_mp_clk 100-150Mhz and MDC clock = l4_mp_clk/62
0x2 l4_mp_clk 25-35Mhz and MDC clock = l4_mp_clk/16
0x3 l4_mp_clk 35-60Mhz and MDC clock = l4_mp_clk/26
0x4 l4_mp_clk 150-250Mhz and MDC clock = l4_mp_clk/102
0x5 l4_mp_clk 250-300Mhz and MDC clock = l4_mp_clk/124
0x8 l4_mp_clk/4
0x9 l4_mp_clk/6
0xa l4_mp_clk/8
0xb l4_mp_clk/10
0xc l4_mp_clk/12
0xd l4_mp_clk/14
0xe l4_mp_clk/16
0xf l4_mp_clk/18
RW 0x0
1 gw

When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register.

Value Description
0x0 GMII Read Operation
0x1 GMII Write Operation
RW 0x0
0 gb

This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. The Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present.

Value Description
0x0 Not Busy
0x1 Busy
RW 0x0