MAC_Frame_Filter

The MAC Frame Filter register contains the filter controls for receiving frames. Some of the controls from this register go to the address check block of the MAC, which performs the first level of address filtering. The second level of filtering is performed on the incoming frame, based on other controls such as Pass Bad Frames and Pass Control Frames.
Module Instance Base Address Register Address
emac0 0xFF700000 0xFF700004
emac1 0xFF702000 0xFF702004

Offset: 0x4

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ra

RW 0x0

Reserved

dntu

RW 0x0

ipfe

RW 0x0

Reserved

vtfe

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

hpf

RW 0x0

saf

RW 0x0

saif

RW 0x0

pcf

RW 0x0

dbf

RW 0x0

pm

RW 0x0

daif

RW 0x0

hmc

RW 0x0

huc

RW 0x0

pr

RW 0x0

MAC_Frame_Filter Fields

Bit Name Description Access Reset
31 ra

When this bit is set, the MAC Receiver block passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver block passes only those frames to the Application that pass the SA or DA address filter.

Value Description
0x0 Receive All off
0x1 Receive All On
RW 0x0
21 dntu

When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames.

Value Description
0x0 Forward all non-TCP or UDP over IP frames
0x1 Drop non-TCP or UDP over IP frames
RW 0x0
20 ipfe

When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 filters.

Value Description
0x0 Forward all frames irrespective of the match status of Layer 3 and Layer 4 filters
0x1 Drop frames that do not match the enabled Layer 3 and Layer 4 filters
RW 0x0
16 vtfe

When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag.

Value Description
0x0 Forward all frames irrespective of the match status of the VLAN tag
0x1 Drop VLAN tagged frames that do not match the VLAN Tag comparison
RW 0x0
10 hpf

When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter.

Value Description
0x0 Hash or Perfect Filter off
0x1 Hash or Perfect Filter on
RW 0x0
9 saf

When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison matches, then the SA Match bit of RxStatus Word is set high. When this bit is set high and the SA filter fails, the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application and with the updated SA Match bit of the RxStatus depending on the SA address comparison.

Value Description
0x0 SA Filter Off
0x1 SA Filter On
RW 0x0
8 saif

When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter.

Value Description
0x0 SA Nomatch Fail
0x1 SA Match Fail
RW 0x0
7:6 pcf

These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). * 00: MAC filters all control frames from reaching the application. * 01: MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter. * 10: MAC forwards all control frames to application even if they fail the Address Filter. * 11: MAC forwards control frames that pass the Address Filter. The following conditions should be true for the PAUSE control frames processing: * Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. * Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. * Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the PAUSE frame filtering may be inconsistent. When Condition 1 is false, the PAUSE frames are considered as generic control frames. Therefore, to pass all control frames (including PAUSE control frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application).

Value Description
0x0 MAC filters all control frames
0x1 MAC forwards all control frames except PAUSE
0x2 MAC forwards all control frames fail addrflt
0x3 MAC forwards control frames that pass addrflt
RW 0x0
5 dbf

When this bit is set, the AFM block filters all incoming broadcast frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM block passes all received broadcast frames.

Value Description
0x0 Pass All Broadcast Frames
0x1 Filter All Broadcast Frames
RW 0x0
4 pm

When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit.

Value Description
0x0 Allows Filter of MC Frames
0x1 All Rcvd MC Frames Pass
RW 0x0
3 daif

When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed.

Value Description
0x0 Normal Inverse Filter
0x1 Address Check Block Inverse Filter
RW 0x0
2 hmc

When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers.

Value Description
0x0 MAC Filters with Compare
0x1 MAC Filters with Hash Table
RW 0x0
1 huc

When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers.

Value Description
0x0 MAC Filters with Compare
0x1 MAC Filters with Hash Table
RW 0x0
0 pr

When this bit is set, the Address Filter block passes all incoming frames regardless of its destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set.

Value Description
0x0 Clear SA DA Status Bits
0x1 All Incoming Frames Passed
RW 0x0