Details different bus operating modes.
Module Instance Base Address Register Address
sdmmc 0xFF704000 0xFF704080

Offset: 0x80

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RO 0x0


RW 0x0


RW 0x0


RW 0x0


RW 0x0

bmod Fields

Bit Name Description Access Reset
10:8 pbl

These bits indicate the maximum number of beats to be performed in one IDMAC transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.

Value Description
0x0 Transfer 1
0x1 Transfer 4
0x2 Transfer 8
0x3 Transfer 16
0x4 Transfer 32
0x5 Transfer 64
0x6 Transfer 128
0x7 Transfer 256
RO 0x0
7 de

Enables and Disables Internal DMA.

Value Description
0x1 IDMAC Enable
0x0 IDMAC Disable
RW 0x0
6:2 dsl

Specifies the number of HWord/Word/Dword (depending on 16/32/64-bit bus) to skip between two unchained descriptors.

RW 0x0
1 fb

Controls whether the AHB Master interface performs fixed burst transfers or not. Will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers.

Value Description
0x1 AHB Master Fixed Burst
0x0 Non Fixed Burst - default
RW 0x0
0 swr

This bit resets all internal registers of the DMA Controller. It is automatically cleared after 1 clock cycle.

Value Description
0x1 Resets DMA Internal Registers
0x0 No reset - default
RW 0x0