Module Instance Base Address Register Address
nandregs 0xFFB80000 0xFFB80780

Offset: 0x780

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x1



RW 0x0

chip_interleave_enable_and_allow_int_reads Fields

Bit Name Description Access Reset
4 allow_int_reads_within_luns

This bit informs the controller to enable or disable simultaneous read accesses to different LUNS in the same bank. This bit is of importance only if the controller supports interleaved operations among LUNs and if the device has multiple LUNS. If the bit is disabled, the controller will send read commands to different LUNS of of the same bank only sequentially and if enabled, the controller will issue simultaneous read accesses to LUNS of same bank if required. [list][*]1 - Enable [*]0 - Disable[/list]

RW 0x1
0 chip_interleave_enable

This bit informs the controller to enable or disable interleaving among banks/LUNS to increase the net performance of the controller. [list][*]1 - Enable interleaving [*]0 - Disable Interleaving[/list]

RW 0x0