Module Instance Base Address Register Address
nandregs 0xFFB80000 0xFFB80100

Offset: 0x100

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x14



RW 0x32

twhr2_and_we_2_re Fields

Bit Name Description Access Reset
13:8 twhr2

Signifies the number of controller clocks that should be introduced between the last command of a random data output command to the start of the data transfer.

RW 0x14
5:0 we_2_re

Signifies the number of bus interface nand_mp_clk clocks that should be introduced between write enable going high to read enable going low. The number of clocks is the function of device parameter Twhr and controller clock frequency.

RW 0x32