Sets the block issuing capability to one outstanding transaction.
Module Instance Base Address Register Address
l3regs 0xFF800000 0xFF820044

Offset: 0x20044

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0


RW 0x0

ahb_cntl Fields

Bit Name Description Access Reset
1 force_incr

Value Description
0x0 Multiple outstanding write transactions
0x1 If a beat is received that has no write data strobes set, that write data beat is replaced with an IDLE beat. Also, causes all transactions that are to be output to the AHB domain to be an undefined length INCR.
RW 0x0
0 decerr_en

Value Description
0x0 No DECERR response.
0x1 If the AHB protocol conversion function receives an unaligned address or a write data beat without all the byte strobes set, creates a DECERR response.
RW 0x0