stat

Provides status fields for software for the FPGA Manager. The Mode field tells software what configuration phase the FPGA currently is in. For regular configuration through the PINs or through the HPS, these states map directly to customer configuration documentation. For Configuration Via PCI Express (CVP), the IOCSR configuration is done through the PINS or through HPS. Then the complete configuration is done through the PCI Express Bus. When CVP is being done, InitPhase indicates only IOCSR configuration has completed. CVP_CONF_DONE is available in the CB Monitor for observation by software. The MSEL field provides a read only register for software to read the MSEL value driven from the external pins.
Module Instance Base Address Register Address
fpgamgrregs 0xFF706000 0xFF706000

Offset: 0x0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

msel

RO 0x8

mode

RW 0x5

stat Fields

Bit Name Description Access Reset
7:3 msel

This read-only field allows software to observe the MSEL inputs from the device pins. The MSEL pins define the FPGA configuration mode.

Value Description
0x0 16-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1
0x1 16-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4
0x2 16-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8
0x3 Reserved
0x4 16-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1
0x5 16-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4
0x6 16-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8
0x7 Reserved
0x8 32-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1
0x9 32-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4
0xa 32-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8
0xb Reserved
0xc 32-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1
0xd 32-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4
0xe 32-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8
0xf Reserved
0x10 Reserved
0x11 Reserved
0x12 Reserved
0x13 Reserved
0x14 Reserved
0x15 Reserved
0x16 Reserved
0x17 Reserved
0x18 Reserved
0x19 Reserved
0x1a Reserved
0x1b Reserved
0x1c Reserved
0x1d Reserved
0x1e Reserved
0x1f Reserved
RO 0x8
2:0 mode

Reports FPGA state

Value Description
0x0 FPGA Powered Off
0x1 FPGA in Reset Phase
0x2 FPGA in Configuration Phase
0x3 FPGA in Initialization Phase. In CVP configuration, this state indicates IO configuration has completed.
0x4 FPGA in User Mode
0x5 FPGA state has not yet been determined. This only occurs briefly after reset.
RW 0x5