Contains VCO control signals and other PLL control signals need to be controllable through register. Fields are only reset by a cold reset.
Module Instance Base Address Register Address
clkmgr 0xFFD04000 0xFFD040C4

Offset: 0xC4

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x1


RW 0x0


RW 0x1


RW 0x0

ctrl Fields

Bit Name Description Access Reset
14 saten

Enables saturation behavior.

RW 0x1
13 fasten

Enables fast locking circuit.

RW 0x0
12:1 bwadj

Provides Loop Bandwidth Adjust value.

RW 0x1
0 bwadjen

If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth Adjust field. If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 value of the VCO Control Register. The M divided by 2 is the upper 12 bits (12:1) of the M field in the VCO register.

RW 0x0