FPGA Slaves Accessed Via HPS2FPGA AXI Bridge (hps2fpgaslaves) Address Map

This address space is allocated for FPGA-configured slaves driven by the HPS-to-FPGA bridge master. The L2 cache filters determine how much of this window is visible to the MPU. For more information about the HPS-to-FPGA bridge, refer to the HPS-FPGA Bridges chapter of the Hard Processor System Technical Reference Manual.

Table 1. hps2fpgaslaves Address Range
Module Instance Start Address End Address