CAN0USEFPGA

Selection between HPS Pins and FPGA Interface for CAN0 signals. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance Base Address Register Address
sysmgr 0xFFD08000 0xFFD08700

Offset: 0x700

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

sel

RW 0x0

CAN0USEFPGA Fields

Bit Name Description Access Reset
0 sel

Select connection for CAN0. 0 : CAN0 uses HPS Pins. 1 : CAN0 uses the FPGA Interface.

RW 0x0