portcfg

Each bit of the autopchen field maps to one of the control ports. If a port executes mostly sequential memory accesses, the corresponding autopchen bit should be 0. If the port has highly random accesses, then its autopchen bit should be set to 1.

Module Instance	Base Address	Register Address
`sdr`	`0xFFC20000`	`0xFFC2507C`

Offset: 0x507C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`												`autopchen` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`autopchen` `RW 0x0`						`Reserved`				`portprotocol` `RO 0x0`

portcfg Fields

Bit

Name

Description

Access

Reset

19:10

autopchen

Auto-Precharge Enable: One bit is assigned to each control port. For each bit, the encodings are as follows:

Value	Description
0x0	The controller requests an automatic precharge following a bus command completion (close the row automatically)
0x1	The controller attempts to keep a row open. All active ports with random dominated operations should set the `autopchen` bit to 1.

The bits in this field correspond to the control ports as follows:

Bit 9	CPU write
Bit 8	L3 write
Bit 7	CPU read
Bit 6	L3 read
Bit 5	FPGA-to-SDRAM port 5
Bit 4	FPGA-to-SDRAM port 4
Bit 3	FPGA-to-SDRAM port 3
Bit 2	FPGA-to-SDRAM port 2
Bit 1	FPGA-to-SDRAM port 1
Bit 0	FPGA-to-SDRAM port 0

RW

0x0

5:0

portprotocol

Port Protocol: You can read this field to determine the protocol configuration of each of the FPGA-to-SDRAM ports. The bits in this field correspond to the control ports as follows:

Bit 5	FPGA-to-SDRAM port 5
Bit 4	FPGA-to-SDRAM port 4
Bit 3	FPGA-to-SDRAM port 3
Bit 2	FPGA-to-SDRAM port 2
Bit 1	FPGA-to-SDRAM port 1
Bit 0	FPGA-to-SDRAM port 0

When you read the corresponding port bit after the FPGA has been configured, it will have one of the following values:

Value	Protocol Configuration Type
0x1	AXI (reset value for all ports)
0x0	Avalon-MM

Note: The value in this field is only valid after the fabric has been configured.

Note: The AXI protocol requires both a read and a write port. Therefore, you must ensure that AXI ports are allocated in the pairs (port 0, port 1), (port 2, port 3), and (port 4, port 5).

Aside from the requirement noted above, AXI and Avalon-MM ports can be mixed freely.

RO

0x0