lowpwreq

This register instructs the controller to put the DRAM into a power down state. Note that some commands are only valid for certain memory types.

Module Instance	Base Address	Register Address
`sdr`	`0xFFC20000`	`0xFFC25054`

Offset: 0x5054

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`										`selfrfshmask` `RW 0x0`		`selfrshreq` `RW 0x0`	`deeppwrdnmask` `RW 0x0`		`deeppwrdnreq` `RW 0x0`

lowpwreq Fields

Bit	Name	Description	Access	Reset
5:4	`selfrfshmask`	Write a one to each bit of this field to have a self refresh request apply to both chips.	`RW`	`0x0`
3	`selfrshreq`	Write a one to this bit to request the RAM be put into a self refresh state. This bit is treated as a static value so the RAM will remain in self-refresh as long as this register bit is set to a one. This power down mode can be selected for all DRAMs supported by the controller.	`RW`	`0x0`
2:1	`deeppwrdnmask`	Write ones to this register to select which DRAM chip selects will be powered down. Typical usage is to set both of these bits when deeppwrdnreq is set but the controller does support putting a single chip into deep power down and keeping the other chip running.	`RW`	`0x0`
0	`deeppwrdnreq`	Write a one to this bit to request a deep power down. This bit should only be written with LPDDR2 DRAMs, DDR3 DRAMs do not support deep power down.	`RW`	`0x0`