dramintr

This register can enable, disable and clear the SDRAM error interrupts.
Module Instance Base Address Register Address
sdr 0xFFC20000 0xFFC2503C

Offset: 0x503C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

intrclr

RW 0x0

corrdropmask

RW 0x0

dbemask

RW 0x0

sbemask

RW 0x0

intren

RW 0x0

dramintr Fields

Bit Name Description Access Reset
4 intrclr

Writing to this self-clearing bit clears the interrupt signal. Writing to this bit also clears the error count and error address registers: sbecount, dbecount, dropcount, erraddr, and dropaddr.

RW 0x0
3 corrdropmask

Set this bit to a one to mask interrupts for an ECC correction write back needing to be dropped. This indicates a burst of memory errors in a short period of time.

 RW 0x0
2 dbemask

Mask the double bit error interrupt.

 RW 0x0
1 sbemask

Mask the single bit error interrupt.

 RW 0x0
0 intren

Enable the interrupt output.

 RW 0x0