dramtiming2

This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor.

Module Instance	Base Address	Register Address
`sdr`	`0xFFC20000`	`0xFFC25008`

Offset: 0x5008

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`			`twtr` `RW 0x0`				`twr` `RW 0x0`				`trp` `RW 0x0`				`trcd` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`trcd` `RW 0x0`			`trefi` `RW 0x0`

dramtiming2 Fields

Bit	Name	Description	Access	Reset
28:25	`twtr`	The write to read timing parameter.	`RW`	`0x0`
24:21	`twr`	The write recovery timing.	`RW`	`0x0`
20:17	`trp`	The precharge to activate timing parameter.	`RW`	`0x0`
16:13	`trcd`	The activate to read/write timing parameter.	`RW`	`0x0`
12:0	`trefi`	The refresh interval timing parameter.	`RW`	`0x0`