IF1CMR

The control bits of the IF1/2 Command Register specify the transfer direction and select which portions of the Message Object should be transferred. A message transfer is started as soon as the CPU has written the message number to the low byte of the Command Request Register and IFxCMR.AutoInc is zero. With this write operation, the IFxCMR.Busy bit is automatically set to 1 to notify the CPU that a transfer is in progress. After a wait time of 2 to 8 HOST_CLK periods, the transfer between theInterface Register and the Message RAM has been completed and the IFxCMR.Busy bit is cleared to 0. The upper limit of the wait time occurs when the message transfer coincides with a CAN message transmission, acceptance filtering, or message storage. If the CPU writes to both Command Registers consecutively (requests a second transfer while another transfer is already in progress), the second transfer starts when the first one is completed. Note: While Busy bit of IF1/2 Command Register is one, IF1/2 Register Set is write protected.
Module Instance Base Address Register Address
can0 0xFFC00000 0xFFC00100
can1 0xFFC01000 0xFFC01100

Offset: 0x100

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

ClrAutoInc

RW 0x0

Reserved

WR1RD0

RW 0x0

Mask

RW 0x0

Arb

RW 0x0

Control

RW 0x0

ClrIntPnd

RW 0x0

TxRqstNewDat

RW 0x0

DataA

RW 0x0

DataB

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Busy

RO 0x0

DMAactive

RW 0x0

AutoInc

RW 0x0

Reserved

MONum

RW 0x1

IF1CMR Fields

Bit Name Description Access Reset
29 ClrAutoInc

Clear the AutoInc bit without starting a transfer

Value Description
0x0 Has no effect to the other Bits of this Register.
0x1 Clear the AutoInc bit without starting a transfer, all other bits will be ignored.
RW 0x0
23 WR1RD0

Write / Read Transfer

Value Description
0x0 Transfer data from the Message Object addressed by IFxCMR.MONum into the selected IFx Message Buffer Registers.
0x1 Transfer data from the selected IFx Message Buffer Registers to the Message Object addressed by IFxCMR.MONum.
RW 0x0
22 Mask

Write Direction: 0= Mask bits unchanged. 1= transfer Identifier Mask + MDir + MXtd to Message Object. Read Direction: 0= Mask bits unchanged. 1= transfer Identifier Mask + MDir + MXtd to IFxMSK Register.

RW 0x0
21 Arb

Write Direction: 0= Arbitration bits unchanged. 1= transfer Identifier + Dir + Xtd + MsgVal to Message Object. Read Direction: 0= Arbitration bits unchanged. 1= transfer Identifier + Dir + Xtd + MsgVal to IFxARB Register.

RW 0x0
20 Control

Write Direction: 0= Control Bits unchanged. 1= transfer Control Bits to Message Object. Note: If IFxCMR.TxRqst/NewDat bit is set, bits IFxMCTR.TxRqst and IFxMCTR.NewDat will be ignored. Read Direction: 0= Control Bits unchanged. 1= transfer Control Bits to IFxMCTR Register.

RW 0x0
19 ClrIntPnd

Write Direction: Has no influence to Message Object at write transfer. Note: When writing to a Message Object, this bit is ignored and copying of IntPnd flag from IFx Control Register to Message RAM could only be controlled by IFxMTR.IntPnd bit. Read Direction: 0= IntPnd bit remains unchanged. 1= clear IntPnd bit in the Message Object.

RW 0x0
18 TxRqstNewDat

Write Direction: 0= TxRqst and NewDat bit will be handled according IFxMCTR.NewDat bit and IFxMCTR.TxRqst bit. 1= set TxRqst and NewDat in Message Object to one Note: If a CAN transmission is requested by setting IFxCMR.TxRqst/NewDat, the TxRqst and NewDat bits in the Message Object will be set to one independently of the values in IFxMCTR. Read Direction: 0= NewDat bit remains unchanged. 1= clear NewDat bit in the Message Object. Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFxMCTR always reflect the status before resetting them.

RW 0x0
17 DataA

Write Direction: 0= Data Bytes 0-3 unchanged. 1= transfer Data Bytes 0-3 to Message Object. Read Direction: 0= Data Bytes 0-3 unchanged. 1= transfer Data Bytes 0-3 to IFxDA.

RW 0x0
16 DataB

Write Direction: 0= Data Bytes 4-7 unchanged. 1= transfer Data Bytes 4-7 to Message Object. Read Direction: 0= Data Bytes 4-7 unchanged. 1= transfer Data Bytes 4-7 to IFxDB. Note: The speed of the message transfer does not depend on how many bytes are transferred.

RW 0x0
15 Busy

Busy Flag

Value Description
0x0 Set to zero when read/write action has finished.
0x1 Set to one when writing to the IFxCMR.MONum. While bit is one, IFx Register Set is write protected.
RO 0x0
14 DMAactive

Activation of DMA feature for subsequent internal IFx Register Set

Value Description
0x0 DMA line leaves passive, independent of IFx activities.
0x1 By writing to the Command Request Register, an internal transfer of Message Object Data between RAM and IFx will be initiated. When this transfer is complete and DMAactive bit was set, the CAN_IFxDMA line gets active. The DMAactive bit and port CAN_IFxDMA are staying active until first read or write access to one of the IFx registers. If AutoInc is set DMAactive will be left active, otherwise the bit is reset. Note: Due to auto reset feature of DMAactive bit if AutoInc is inactive, this bit has to be set for each subsequent DMA cycle separately. DMA line has to be enabled in CAN Control Register.
RW 0x0
13 AutoInc

Automatic Increment of Message Object Number The behavior of the Message Object Number increment depends on the Transfer Direction, IFxCMR.WR1RD0. * Read: The first transfer will be initiated (Busy Bit will set) at write of IFxCMR.MONum. The Message Object Number will be incremented and the next Message Object will be transferred from Message Object RAM to Interface Registers after a read access of Data-Byte 7. * Write: The first as well as each other transfer will be started after write access to Data- Byte7. The Message Object Number will be incremented after successful transfer from the Interface Registers to the Message Object RAM. Always after successful transfer the Busy Bit will be reset. In combination with DMAactive the port CAN_IFxDMA is set, too. Note: If the direction is configured as Read a write access to Data-Byte 7 will not start any transfer, as well as if the direction is configured as Write a read access to Data-Byte 7 will not start any transfer. At transfer direction Read each read of Data-Byte 7 will start a transfer until IFxCMR.AutoInc is reset. To aware of resetting a NewDat bit of the following message object, the application has to reset IFxCMR.AutoInc before reading the Data-Byte 7 of the last message object which will be read.

Value Description
0x0 AutoIncrement of Message Object Number disabled.
0x1 AutoIncrement of Message Object Number enabled.
RW 0x0
7:0 MONum

0x01-0x80 Valid Message Number, the Message Object in the Message RAM is selected for data transfer (up to 128 MsgObj). 0x00 Not a valid Message Number, interpreted as 0x80. 0x81-0xFF Not a valid Message Number, interpreted as 0x01-0x7F. Note: When an invalid Message Number is written to IFxCMR.MONum which is higher than the last Message Object number, a modulo addressing will occur.When e.g. accessing Message Object 33 in a CAN module with 32 Message Objects only, the Message Object 1 will be accessed instead.

RW 0x1