CRR

Core Release Register

Module Instance	Base Address	Register Address
`can0`	`0xFFC00000`	`0xFFC00020`
`can1`	`0xFFC01000`	`0xFFC01020`

Offset: 0x20

Access: RO

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`REL` `RO 0x1`				`STEP` `RO 0x11`								`YEAR` `RO 0x6`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`MON` `RO 0x11`								`DAY` `RO 0x28`

CRR Fields

Bit	Name	Description	Access	Reset
31:28	`REL`		`RO`	`0x1`
27:20	`STEP`		`RO`	`0x11`
19:16	`YEAR`		`RO`	`0x6`
15:8	`MON`		`RO`	`0x11`
7:0	`DAY`		`RO`	`0x28`