CCTRL

Control Register
Module Instance Base Address Register Address
can0 0xFFC00000 0xFFC00000
can1 0xFFC01000 0xFFC01000

Offset: 0x0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

DE2

RW 0x0

DE1

RW 0x0

MIL

RW 0x0

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Test

RW 0x0

CCE

RW 0x0

DAR

RW 0x0

Reserved

EIE

RW 0x0

SIE

RW 0x0

ILE

RW 0x0

Init

RW 0x1

CCTRL Fields

Bit Name Description Access Reset
19 DE2

DMA Enable for IF2

Value Description
0x0 Module DMA output port CAN_IF2DMA is always LOW.
0x1 Requesting a message object transfer from IF2 to Message RAM or vice versa with IF2CMR.DMAactive enabled the end of the transfer will be marked with setting port CAN_IF2DMA to one. The port remains one until first access to one of the IF2 registers.
RW 0x0
18 DE1

DMA Enable for IF1

Value Description
0x0 Module DMA output port CAN_IF1DMA is always LOW.
0x1 Requesting a message object transfer from IF1 to Message RAM or vice versa with IF1CMR.DMAactive enabled the end of the transfer will be marked with setting port CAN_IF1DMA to one. The port remains one until first access to one of the IF1 registers.
RW 0x0
17 MIL

Message Object Interrupt Line Enable

Value Description
0x0 Message Object Interrupt CAN_INT_MO is always LOW. If CCTRL.ILE is enabled all message object interrupts are routed to line CAN_INT_STATUS otherwise no message object interrupt will be visible.
0x1 Message object interrupts will set CAN_INT_MO to one, signal remains one until all pending interrupts are processed.
RW 0x0
7 Test

Test Mode Enable

Value Description
0x0 Normal Operation.
0x1 Test Mode. Enables the write access to Test Register CTR.
RW 0x0
6 CCE

Configuration Change Enable

Value Description
0x0 The CPU has no write access to the configuration registers.
0x1 The CPU has write access to the Bit Timing Register CBT (while CCTRL.Init = 1).
RW 0x0
5 DAR

Disable Automatic Retransmission

Value Description
0x0 Automatic Retransmission of not successful messages enabled.
0x1 Automatic Retransmission disabled.
RW 0x0
3 EIE

Error Interrupt Enable

Value Description
0x0 CSTS.PER, CSTS.BOff and CSTS.EWarn flags will still be updated, but without affecting interrupt line CAN_INT_STATUS and Interrupt register CIR
0x1 If CSTS.PER flag is one, or CSTS.BOff or CSTS.EWarn are changed, the interrupt line CAN_INT_STATUS gets active (if ILE=1) and CIR.StatusInt is set.
RW 0x0
2 SIE

Status Interrupt Enable

Value Description
0x0 CSTS.RxOk, CSTS.TxOk and CSTS.LEC will still be updated, but without affecting interrupt line CAN_INT_STATUS and Interrupt register CIR.
0x1 When a message transfer is successfully completed or a CAN bus error is detected, indicated by flags CSTS.RxOk, CSTS.TxOk and CSTS.LEC, the interrupt line CAN_INT_STATUS gets active (if ILE=1) and CIR.StatusInt is set.
RW 0x0
1 ILE

Module Interrupt Line Enable

Value Description
0x0 Module Interrupt Line CAN_INT_STATUS is always LOW.
0x1 Error and status interrupts (if CCTRL.EIE=1 and CCTRL.SIE=1) will set line CAN_INT_STATUS to one, signal remains one until all pending interrupts are processed. If MIL is disabled, the message object interrupts will also affect this interrupt line.
RW 0x0
0 Init

Initialization Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to CCTRL.Init can be read back. Therefore the programmer has to assure that the previous value written to CCTRL.Init has been accepted by reading CCTRL.Init before setting CCTRL.Init to a new value.\n Note: The Bus_Off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or resetting CCTRL.Init. If the device goes Bus_Off, it will set CCTRL.Init of its own accord, stopping all bus activities. Once CCTRL.Init has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operations. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCTRL.Init, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to the Status Register, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the proceeding of the us_Off recovery sequence.

Value Description
0x0 Normal Operation.
0x1 Initialization is started.
RW 0x1