timersrawintstat

Provides the interrupt status for all timers before masking. Note that there is only Timer1 in this module instance.
Module Instance Base Address Register Address
sptimer0 0xFFC08000 0xFFC080A8
sptimer1 0xFFC09000 0xFFC090A8
osc1timer0 0xFFD00000 0xFFD000A8
osc1timer1 0xFFD01000 0xFFD010A8

Offset: 0xA8

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

timersrawintstat

RO 0x0

timersrawintstat Fields

Bit Name Description Access Reset
0 timersrawintstat

Provides the interrupt status for Timer1. Because there is only Timer1 in this module instance, this status is the same as timer1intstat. The status reported is before the interrupt mask has been applied. Reading from this register does not clear any active interrupts.

Value Description
0x0 Timer1 interrupt is not active
0x1 Timer1 interrupt is active
RO 0x0