gpio_swporta_ddr

This register establishes the direction of each corresponding GPIO Data Field Bit. Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
Module Instance Base Address Register Address
gpio0 0xFF708000 0xFF708004
gpio1 0xFF709000 0xFF709004
gpio2 0xFF70A000 0xFF70A004

Offset: 0x4

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

gpio_swporta_ddr

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

gpio_swporta_ddr

RW 0x0

gpio_swporta_ddr Fields

Bit Name Description Access Reset
28:0 gpio_swporta_ddr

Values written to this register independently control the direction of the corresponding data bit in the Port A Data Register. Note that only bits[26:0] are implemented for gpio2.

Value Description
0x0 Input Direction
0x1 Output Direction
RW 0x0