sfe
This is a shadow register for the FIFO enable bit [0] of register FCR.
| Module Instance | Base Address | Register Address |
|---|---|---|
| uart0 | 0xFFC02000 | 0xFFC02098 |
| uart1 | 0xFFC03000 | 0xFFC03098 |
Offset: 0x98
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
sfe RW 0x0 |
||||||||||||||
sfe Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | sfe | This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated. This enables/disables the transmit (Tx) and receive (Rx ) FIFO's. If this bit is set to zero (disabled) after being enabled then both the Tx and Rx controller portion of FIFO's will be reset.
|
RW | 0x0 |