far
This register is used in FIFO access testing.
| Module Instance | Base Address | Register Address |
|---|---|---|
| uart0 | 0xFFC02000 | 0xFFC02070 |
| uart1 | 0xFFC03000 | 0xFFC03070 |
Offset: 0x70
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
srbr_sthr RW 0x0 |
||||||||||||||
far Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | srbr_sthr | This register is used to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFO's are enabled. When FIFO's are not enabled it allows the RBR to be written by the master and the THR to be read by the master Note: That when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty.
|
RW | 0x0 |