sthr

Used to accomadate burst accesses from the master.

Module Instance	Base Address	Register Address
`uart0`	`0xFFC02000`	`0xFFC02034`
`uart1`	`0xFFC03000`	`0xFFC03034`

Offset: 0x34

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`sthr` `RW 0x0`

sthr Fields

Bit	Name	Description	Access	Reset
7:0	`sthr`	This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout). Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled bit [0] of register FCR set to zero and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled bit [0] of register FCR set to one and THRE is set, 128 characters of data may be written to the THR before the FIFO is full. The UART FIFO depth is configured for 128 characters. Any attempt to write data when the FIFO is full results in the write data being lost.	`RW`	`0x0`