icr

Module Instance Base Address Register Address
spis0 0xFFE02000 0xFFE02048
spis1 0xFFE03000 0xFFE03048

Offset: 0x48

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

icr

RO 0x0

icr Fields

Bit Name Description Access Reset
0 icr

This register is set if any of the interrupts below are active. A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts. Writing to this register has no effect.

RO 0x0