risr

This register reports the status of the SPI Master interrupts prior to masking.
Module Instance Base Address Register Address
spim0 0xFFF00000 0xFFF00034
spim1 0xFFF01000 0xFFF01034

Offset: 0x34

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

rxfir

RO 0x0

rxoir

RO 0x0

rxuir

RO 0x0

txoir

RO 0x0

txeir

RO 0x0

risr Fields

Bit Name Description Access Reset
4 rxfir

The interrupt is active or inactive prior to masking.

Value Description
0x0 spi_rxf_intr interrupt is not active prior to masking
0x1 spi_rxf_intr interrupt is active prior to masking
RO 0x0
3 rxoir

The interrupt is active or inactive prior to masking.

Value Description
0x0 spi_rxo_intr interrupt is not active prior to masking
0x1 spi_rxo_intr interrupt is active prior masking
RO 0x0
2 rxuir

The interrupt is active or inactive prior to masking.

Value Description
0x0 spi_rxu_intr interrupt is not active prior to masking
0x1 spi_rxu_intr interrupt is active prior to masking
RO 0x0
1 txoir

The interrupt is active or inactive prior to masking.

Value Description
0x0 spi_txo_intr interrupt is not active prior to masking
0x1 spi_txo_intr interrupt is active prior masking
RO 0x0
0 txeir

The interrupt is active or inactive prior to masking.

Value Description
0x0 spi_txe_intr interrupt is not active prior to masking
0x1 spi_txe_intr interrupt is active prior masking
RO 0x0