sr

This register is used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. The status register may be read at any time. None of the bits in this register request an interrupt.
Module Instance Base Address Register Address
spim0 0xFFF00000 0xFFF00028
spim1 0xFFF01000 0xFFF01028

Offset: 0x28

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

rff

RO 0x0

rfne

RO 0x0

tfe

RO 0x1

tfnf

RO 0x1

busy

RO 0x0

sr Fields

Bit Name Description Access Reset
4 rff

Reports receive FIFO condition.

Value Description
0x0 Receive FIFO is not full
0x1 Receive FIFO is full
RO 0x0
3 rfne

Reports receive FIFO condition.

Value Description
0x0 Receive FIFO is empty
0x1 Receive FIFO is not empty
RO 0x0
2 tfe

Reports transmit FIFO condition.

Value Description
0x1 Transmit FIFO is empty
0x0 Transmit FIFO is not empty
RO 0x1
1 tfnf

Reports transmit FIFO condition.

Value Description
0x0 Transmit FIFO is full
0x1 Transmit FIFO is not full
RO 0x1
0 busy

Reports the staus of a serial transfer

Value Description
0x0 SPI Master is inactive (idle or disabled)
0x1 SPI Master is actively transferring data
RO 0x0