ctrlr1
Control register 1 controls the end of serial transfers when in receive-only mode. It is impossible to write to this register when the SPI Master is enabled.The SPI Master is enabled and disabled by writing to the SPIENR register.
| Module Instance | Base Address | Register Address |
|---|---|---|
| spim0 | 0xFFF00000 | 0xFFF00004 |
| spim1 | 0xFFF01000 | 0xFFF01004 |
Offset: 0x4
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ndf RW 0x0 |
|||||||||||||||
ctrlr1 Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 15:0 | ndf | When TMOD = 10 or TMOD =11, this register field sets the number of data frames to be continuously received by the SPI Master. The SPI Master continues to receive serial data until the number of data frames received is equal to this register value plus 1, which enables you to receive up to 64 KB of data in a continuous transfer. |
RW | 0x0 |