diepint12

This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00A88
usb1 0xFFB40000 0xFFB40A88

Offset: 0xA88

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

nyetintrpt

RO 0x0

nakintrpt

RO 0x0

bbleerr

RO 0x0

pktdrpsts

RO 0x0

Reserved

bnaintr

RO 0x0

txfifoundrn

RO 0x0

txfemp

RO 0x1

inepnakeff

RO 0x0

intknepmis

RO 0x0

intkntxfemp

RO 0x0

timeout

RO 0x0

ahberr

RO 0x0

epdisbld

RO 0x0

xfercompl

RO 0x0

diepint12 Fields

Bit Name Description Access Reset
14 nyetintrpt

The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Value Description
0x0 No interrupt
0x1 NYET Interrupt
RO 0x0
13 nakintrpt

The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.

Value Description
0x0 No interrupt
0x1 NAK Interrupt
RO 0x0
12 bbleerr

The core generates this interrupt when babble is received for the endpoint.

Value Description
0x0 No interrupt
0x1 BbleErr interrupt
RO 0x0
11 pktdrpsts

This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.

Value Description
0x0 No interrupt
0x1 Packet Drop Status interrupt
RO 0x0
9 bnaintr

This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done

Value Description
0x0 No interrupt
0x1 BNA interrupt
RO 0x0
8 txfifoundrn

Applies to IN endpoints Only. The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint.

Value Description
0x0 No interrupt
0x1 Fifo Underrun interrupt
RO 0x0
7 txfemp

This bit is valid only for IN Endpoints This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Value Description
0x0 No interrupt
0x1 Transmit FIFO Empty interrupt
RO 0x1
6 inepnakeff

Applies to periodic IN endpoints only. This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This interrupt indicates that the core has sampled the NAK bit Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Value Description
0x0 No interrupt
0x1 IN Endpoint NAK Effective interrupt
RO 0x0
5 intknepmis

Applies to non-periodic IN endpoints only. Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

Value Description
0x0 No interrupt
0x1 IN Token Received with EP Mismatch interrupt
RO 0x0
4 intkntxfemp

Applies to non-periodic IN endpoints only. Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

Value Description
0x0 No interrupt
0x1 IN Token Received Interrupt
RO 0x0
3 timeout

In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

Value Description
0x0 No interrupt
0x1 Timeout interrupy
RO 0x0
2 ahberr

Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.

Value Description
0x0 No Interrupt
0x1 AHB Error interrupt
RO 0x0
1 epdisbld

Applies to IN and OUT endpoints. This bit indicates that the endpoint is disabled per the application's request.

Value Description
0x0 No Interrupt
0x1 Endpoint Disabled Interrupt
RO 0x0
0 xfercompl

Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled - for IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO. - for OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Value Description
0x0 No Interrupt
0x1 Transfer Completed Interrupt
RO 0x0