dieptsiz8

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00A10
usb1 0xFFB40000 0xFFB40A10

Offset: 0xA10

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

mc

RW 0x0

pktcnt

RW 0x0

xfersize

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

xfersize

RW 0x0

dieptsiz8 Fields

Bit Name Description Access Reset
30:29 mc

for periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)

Value Description
0x1 1 packet
0x2 2 packets
0x3 3 packets
RW 0x0
28:19 pktcnt

Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

RW 0x0
18:0 xfersize

Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be Set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the TxFIFO.

RW 0x0