dctl

Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00804
usb1 0xFFB40000 0xFFB40804

Offset: 0x804

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

nakonbble

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ignrfrmnum

RW 0x0

gmc

RW 0x0

Reserved

pwronprgdone

RW 0x0

cgoutnak

WO 0x0

sgoutnak

WO 0x0

CGNPInNak

WO 0x0

sgnpinnak

WO 0x0

tstctl

RW 0x0

goutnaksts

RO 0x0

gnpinnaksts

RO 0x0

sftdiscon

RW 0x0

rmtwkupsig

RW 0x0

dctl Fields

Bit Name Description Access Reset
16 nakonbble

Set NAK automatically on babble (NakOnBble). The core sets NAK automatically for the endpoint on which babble is received.

Value Description
0x0 Disable NAK on Babble Error
0x1 NAK on Babble Error
RW 0x0
15 ignrfrmnum

Do NOT program IgnrFrmNum bit to 1'b1 when the core is operating in threshold mode. When Scatter/Gather DMA mode is enabled this feature is not applicable to High Speed, High bandwidth transfers. When this bit is enabled, there must be only one packet per descriptor. In Scatter/Gather DMA mode, if this bit is enabled, the packets are not flushed when a ISOC IN token is received for an elapsed frame. When Scatter/Gather DMA mode is disabled, this field is used by the application to enable periodic transfer interrupt. The application can program periodic endpoint transfers for multiple (micro)frames. 0: periodic transfer interrupt feature is disabled, application needs to program transfers for periodic endpoints every (micro)frame 1: periodic transfer interrupt feature is enabled, application can program transfers for multiple (micro)frames for periodic endpoints. In non Scatter/Gather DMA mode the application will receive transfer complete interrupt after transfers for multiple (micro)frames are completed.

Value Description
0x0 The core transmits the packets only in the frame number in which they are intended to be transmitted
0x1 The core ignores the frame number, sending packets immediately as the packets are ready
RW 0x0
14:13 gmc

GMC must be programmed only once after initialization.Applicable only for Scatter/Gather DMA mode. This indicates the number of packets to be serviced for that end point before moving to the next end point. It is only for non-periodic end points. When Scatter/Gather DMA mode is disabled, this field isreserved. and reads 0.

Value Description
0x0 Invalid
0x1 1 packet
0x2 2 packets
0x3 3 packets
RW 0x0
11 pwronprgdone

The application uses this bit to indicate that registerprogramming is completed after a wake-up from Power Downmode.

Value Description
0x0 Power-On Programming not done
0x1 Power-On Programming Done
RW 0x0
10 cgoutnak

A write to this field clears the Global OUT NAK.

Value Description
0x0 Disable Clear Global OUT NAK
0x1 Clear Global OUT NAK
WO 0x0
9 sgoutnak

A write to this field sets the Global OUT NAK.The application uses this bit to send a NAK handshake on all OUT endpoints. The application must Set the this bit only after making sure that the Global OUT NAK Effective bit in the Core Interrupt Register GINTSTS.GOUTNakEff) is cleared.

Value Description
0x0 Disable Global OUT NAK
0x1 Global OUT NAK
WO 0x0
8 CGNPInNak

A write to this field clears the Global Non-periodic IN NAK.

Value Description
0x0 Disable Global Non-periodic IN NAK
0x1 Clear Global Non-periodic IN NAK
WO 0x0
7 sgnpinnak

A write to this field sets the Global Non-periodic IN NAK. The application uses this bit to send a NAK handshake on all nonperiodic IN endpoints. The core can also Set this bit when a timeout condition is detected on a non-periodic endpoint in shared FIFO operation. The application must Set this bit only after making sure that the Global IN NAK Effective bit in the Core Interrupt Register (GINTSTS.GINNakEff) is cleared

Value Description
0x0 Disable Global Non-periodic IN NAK
0x1 Global Non-periodic IN NAK
WO 0x0
6:4 tstctl

Others: Reserved.

Value Description
0x0 Test mode disabled
0x1 Test_J mode
0x2 Test_K mode
0x3 Test_SE0_NAK mode
0x4 Test_Packet mode
0x5 Test_force_Enable
RW 0x0
3 goutnaksts

Reports NAK status. All isochronous OUT packets aredropped.

Value Description
0x0 A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.
0x1 No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped.
RO 0x0
2 gnpinnaksts

Defines IN NAK conditions.

Value Description
0x0 A handshake is sent out based on the data availability in the transmit FIFO
0x1 A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO.
RO 0x0
1 sftdiscon

The application uses this bit to signal the otg core to do a soft disconnect. As long as this bit is Set, the host does not see that the device is connected, and the device does not receive signals on the USB. The core stays in the disconnected state until the application clears this bit. There is a minimum duration for which the core must keep this bit set. When this bit is cleared after a soft disconnect, the core drives the phy_opmode_o signal on the ULPI, which generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration.;

Value Description
0x0 Normal operation
0x1 The core drives the phy_opmode_o signal on the ULPI
RW 0x0
0 rmtwkupsig

When the application sets this bit, the core initiates remote signaling to wake up the USB host. The application must Set this bit to instruct the core to exit the Suspend state. As specified in the USB 2.0 specification, the application must clear this bit 115 ms after setting it. Remote Wakeup Signaling (RmtWkUpSig) When LPM is enabled, In L1 state the behavior of this bit is as follows: When the application sets this bit, the core initiates L1 remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the Sleep state. As specified in the LPM specification, the hardware will automatically clear this bit after a time of 50us (TL1DevDrvResume) after set by application. Application should not set this bit when GLPMCFG bRemoteWake from the previous LPM transaction was zero.

Value Description
0x0 No exit suspend state
0x1 Exit Suspend State
RW 0x0