hprt

Indicates the speed of the device attached to this port.

The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port.

The application uses this field to control power to this port, and the core can clear this bit on an over current condition.

Indicates the current logic level USB data lines. Bit [10]: Logic level of D+ Bit [11]: Logic level of D-

When the application sets this bit, a reset sequence is started on this port. The application must time the reset period and clear this bit after the reset sequence is complete. The application must leave this bit Set for at least a minimum duration mentioned below to start a reset on the port. The application can leave it Set for another 10 ms in addition to the required minimum duration, before clearing the bit, even though there is no maximum limit set by theUSB standard. This bit is cleared by the core even if there is no device connected to the Host. High speed: 50 ms Full speed/Low speed: 10 ms

The application sets this bit to put this port in Suspend mode. The core only stops sending SOFs when this is Set. To stop the PHY clock, the application must Set the Port Clock Stop bit, which asserts the suspend input pin of the PHY. The read value of this bit reflects the current suspend status of the port. This bit is cleared by the core after a remote wakeup signal is detected or the application sets the Port Reset bit or Port Resume bit in this register or the Resume/Remote Wakeup Detected Interrupt bit or Disconnect Detected Interrupt bit in the Core Interrupt register (GINTSTS.WkUpInt or GINTSTS.DisconnInt, respectively). This bit is cleared by the core even if there is no device connected to the Host.

The application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until the application clears this bit. If the core detects a USB remote wakeup sequence, as indicated by the Port Resume/Remote Wakeup Detected Interrupt bit of the Core Interrupt register (GINTSTS.WkUpInt), the core starts driving resume signaling without application intervention and clears this bit when it detects a disconnect condition. The read value of this bit indicates whether the core is currently drivingresume signaling. When LPM is enabled and the core is in the L1 (Sleep) state, setting this bit results in the following behavior: The core continues to drive the resume signal until a pre-determined time specified in the GLPMCFG.HIRD_Thres[3:0] field. If the core detects a USB remote wakeup sequence, as indicated by the Port L1 Resume/Remote L1 Wakeup Detected Interrupt bit of the Core Interrupt register (GINTSTS.L1WkUpInt), the core starts driving resume signaling without application intervention and clears this bit at the end of the resume. The read value of this bit indicates whether the core is currently driving resume signaling.

The core sets this bit when the status of the PortOvercurrent Active bit (bit 4) in this register changes.This bit can be set only by the core and the application should write 1 to clear it

Indicates the overcurrent condition of the port. 0x0: No overcurrent condition 0x1: Overcurrent condition

The core sets this bit when the status of the Port Enable bit [2] of this register changes. This bit can be set only by the core and the application should write 1 to clear it.

A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condition, or by the application clearing this bit. The application cannot Set this bit by a register write. It can only clear it to disable the port by writing 1. This bit does not trigger any interrupt to the application.

The core sets this bit when a device connection is detected to trigger an interrupt to the application using the Host Port Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt). This bit can be set only by the core and the application should write 1 to clear it.The application must write a 1 to this bit to clear the interrupt.

Defines whether port is attached.