hcfg

Host Mode control. This register must be programmed every time the core changes to Host mode

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB00400`
`usb1`	`0xFFB40000`	`0xFFB40400`

Offset: 0x400

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`modechtimen` `RW 0x0`	`Reserved`				`perschedena` `RW 0x0`	`frlisten` `RW 0x0`		`descdma` `RW 0x0`	`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`resvalid` `RW 0x2`								`ena32khzs` `RW 0x0`	`Reserved`				`fslssupp` `RW 0x0`	`fslspclksel` `RW 0x0`

hcfg Fields

Bit

Name

Description

Access

Reset

modechtimen

This bit is used to enable or disable the host core to wait for 200 PHY clock cycles at the end of Resume to change the opmode signal to the PHY to 00 after Suspend or LPM.

Value	Description
0x0	The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end of resume to change the opmode from 0x2 to 0x0
0x1	The Host core waits only for a linestate of SE0 at the end of resume to change the opmode from 0x2 to 0x0

RW

0x0

perschedena

Applicable in Scatter/Gather DMA mode only. Enables periodic scheduling within the core. Initially, the bit is reset. The core will not process any periodic channels. As soon as this bit is set, the core will get ready to start scheduling periodic channels. In non Scatter/Gather DMA mode, this bit is reserved.

Value	Description
0x0	Disables periodic scheduling within the core
0x1	Enables periodic scheduling within the core

RW

0x0

25:24

frlisten

The value in the register specifies the number of entries in the Frame list. This field is valid only in Scatter/Gather DMA mode.

Value	Description
0x0	Reserved
0x1	8 Entries
0x2	16 Entries
0x3	32 Entries

RW

0x0

descdma

The application can set this bit during initialization to enable the Scatter/Gather DMA operation. This bit must be modified only once after a reset. The following combinations are available for programming: GAHBCFG.DMAEn=0,HCFG.DescDMA=0 => Slave mode GAHBCFG.DMAEn=0,HCFG.DescDMA=1 => InvalidGAHBCFG.DMAEn=1,HCFG.DescDMA=0 => Buffered DMA mode GAHBCFG.DMAEn=1,HCFG.DescDMA=1 => Scatter/Gather DMA mode

Value	Description
0x0	No Scatter/Gather DMA
0x1	Scatter/Gather DMA selected

RW

0x0

15:8

resvalid

This field is effective only when HCFG.Ena32KHzS is set. It will control the resume period when the core resumes from suspend. The core counts for ResValid number of clock cycles to detect a valid resume when this is set.

RW

0x2

ena32khzs

This bit can only be set if the USB 1.1 Full-Speed Serial Transceiver Interface has been selected. If USB 1.1 Full-Speed Serial Transceiver Interface has not been selected, this bit must be zero. When the USB 1.1 Full-Speed Serial Transceiver Interface is chosen and this bit is set, the core expects the 48-MHz PHY clock to be switched to 32 KHz during a suspend.

Value	Description
0x0	USB 1.1 Full-Speed Not Selected
0x1	USB 1.1 Full-Speed Serial Transceiver Interface selected

RW

0x0

fslssupp

The application uses this bit to control the core's enumeration speed. Using this bit, the application can make the core enumerate as a FS host, even If the connected device supports HS traffic. Do not make changes to this field after initial programming.

Value	Description
0x0	HS/FS/LS, based on the maximum speed supported by the connected device
0x1	FS/LS-only, even if the connected device can support HS

RW

0x0

1:0

fslspclksel

When the core is in FS Host mode. The internal PHY clock is running at 30/60 MHZ for ULPI PHY Interfaces. The internal PHY clock is running at 48MHZ for 1.1 FS transceiver Interface When the core is in LS Host mode, the internal PHY clock is running at 30/60 MHZ for ULPI PHY Interfaces. The internal PHY clock is running at 6 MHZ and the external clock is running at 48MHZ. When you select a 6 MHz clock during LS Mode, you must do a soft reset for 1.1 FS transceiver Interface. * When Core in FS mode, the internal and external clocks have the same frequency. * When Core in LS mode, - If fslspclksel is 30/60 Mhz internal and external clocks have the same frequency. - If fslspclksel is 6Mhz the internal clock is divided by eight of external 48 MHz clock (utmifs_clk).

Value	Description
0x0	PHY clock is running at 30/60 MHz
0x1	PHY clock is running at 48 MHz
0x2	PHY clock is running at 6 MHz

RW

0x0