ghwcfg2

This register contains configuration options.

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB00048`
`usb1`	`0xFFB40000`	`0xFFB40048`

Offset: 0x48

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`	`tknqdepth` `RO 0x8`					`ptxqdepth` `RO 0x0`		`nptxqdepth` `RO 0x2`		`Reserved`	`multiprocintrpt` `RO 0x0`	`dynfifosizing` `RO 0x1`	`periosupport` `RO 0x1`	`numhstchnl` `RO 0xF`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`numhstchnl` `RO 0xF`		`numdeveps` `RO 0xF`				`fsphytype` `RO 0x0`		`hsphytype` `RO 0x2`		`singpnt` `RO 0x0`	`otgarch` `RO 0x2`		`otgmode` `RO 0x0`

ghwcfg2 Fields

Bit

Name

Description

Access

Reset

30:26

tknqdepth

Range: 0 to 30.

RO

0x8

25:24

ptxqdepth

Specifies the Host mode Periodic Request Queue depth.That is, the maximum number of packets that can reside in the Host Periodic TxFIFO. This queue holds one entry corresponding to each IN or OUT periodic request. This queue is 9 bits wide.

Value	Description
0x0	Que Depth 2
0x1	Que Depth 4
0x2	Que Depth 8
0x3	Que Depth 16

RO

0x0

23:22

nptxqdepth

Specifies the Non-periodic Request Queue depth, the maximum number of packets that can reside in the Non-periodic TxFIFO. In Device mode, the queue is used only in Shared FIFO Mode (Enable Dedicated Transmit FIFO for device IN Endpoints? =No). In this mode, there is one entry in the Non-periodic Request Queue for each packet in the Non-periodic TxFIFO. In Host mode, this queue holds one entry corresponding to each IN or OUT nonperiodic request. This queue is seven bits wide.

Value	Description
0x0	Que size 2
0x1	Que size 4
0x2	Que size 8

RO

0x2

multiprocintrpt

Not implemented.

Value	Description
0x0	No Multi Processor Interrupt Enabled

RO

0x0

dynfifosizing

Feature supported.

Value	Description
0x1	Dynamic FIFO Sizing Enabled

RO

0x1

periosupport

Feature supported.

Value	Description
0x1	Periodic OUT Channels Supported in Host Mode Supported

RO

0x1

17:14

numhstchnl

Indicates the number of host channels supported by the core in Host mode.

Value	Description
0x0	Host Channel 1
0x1	Host Channel 2
0x2	Host Channel 3
0x3	Host Channel 4
0x4	Host Channel 5
0x5	Host Channel 6
0x6	Host Channel 7
0x7	Host Channel 8
0x8	Host Channel 9
0x9	Host Channel 10
0xa	Host Channel 11
0xb	Host Channel 12
0xc	Host Channel 13
0xd	Host Channel 14
0xe	Host Channel 15
0xf	Host Channel 16

RO

0xF

13:10

numdeveps

The number of endpoints is 1 to 15 in Device mode in addition to control endpoint 0.

Value	Description
0x0	End point 0
0x1	End point 1
0x2	End point 2
0x3	End point 3
0x4	End point 4
0x5	End point 5
0x6	End point 6
0x7	End point 7
0x8	End point 8
0x9	End point 9
0xa	End point 10
0xb	End point 11
0xc	End point 12
0xd	End point 13
0xe	End point 14
0xf	End point 15

RO

0xF

9:8

fsphytype

Specifies the Full Speed PHY in use.

Value	Description
0x2	ULPI Type

RO

0x0

7:6

hsphytype

Specifies the High Speed PHY in use.

Value	Description
0x0	High-Speed interface not supported
0x2	ULPI

RO

0x2

singpnt

Single Point Only.

Value	Description
0x1	Single-point applicatio

RO

0x0

4:3

otgarch

DMA Architecture.

Value	Description
0x2	Internal DMA

RO

0x2

2:0

otgmode

HNP- and SRP-Capable OTG (Device and Host).

Value	Description
0x0	HNP- and SRP-Capable OTG (Host & Device
0x1	SRP-Capable OTG (Host & Device)
0x2	Non-HNP and Non-SRP Capable OTG (Host & Device)
0x3	SRP-Capable Device
0x4	Non-OTG Device
0x5	SRP-Capable Host
0x6	Non-OTG Host

RO

0x0