gpvndctl

The application can use this register to access PHY registers. for a ULPI PHY, the core uses the ULPI interface for PHY register access. The application sets Vendor Control register for PHY register access and times the PHY register access. The application polls the VStatus Done bit in this register for the completion of the PHY register access
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00034
usb1 0xFFB40000 0xFFB40034

Offset: 0x34

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

disulpidrvr

RO 0x0

Reserved

vstsdone

RO 0x0

vstsbsy

RO 0x0

newregreq

RW 0x0

Reserved

regwr

RW 0x0

regaddr

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

vctrl

RW 0x0

regdata

RW 0x0

gpvndctl Fields

Bit Name Description Access Reset
31 disulpidrvr

The application sets this bit when it has finished processing the ULPI Carkit Interrupt (GINTSTS.ULPICKINT). When Set, the otg core disables drivers for output signals and masks input signal for the ULPI interface. otg clears this bit before enabling the ULPI interface.

Value Description
0x0 ULPI ouput signals
0x1 Disable ULPI ouput signals
RO 0x0
27 vstsdone

The core sets this bit when the vendor control access isdone. This bit is cleared by the core when the application sets the New Register Request bit (bit 25).

Value Description
0x0 VStatus Done inactive
0x1 VStatus Done active
RO 0x0
26 vstsbsy

The core sets this bit when the vendor control access is in progress and clears this bit when done.

Value Description
0x0 VStatus Busy inactive
0x1 VStatus Busy active
RO 0x0
25 newregreq

The application sets this bit for a new vendor controlaccess.

Value Description
0x0 New Register Request not active
0x1 New Register Request active
RW 0x0
22 regwr

Set this bit for register writes, and clear it for register reads.

Value Description
0x0 Register Read
0x1 Register Write
RW 0x0
21:16 regaddr

The 6-bit PHY register address for immediate PHY Register Set access. Set to 0x2F for Extended PHY Register Set access.

 RW 0x0
15:8 vctrl UTMI+ Vendor Control Register Address (VCtrl): The 4-bit register address a vendor defined 4-bit parallel output bus. Bits 11:8 of this field are placed on utmi_vcontrol[3:0].

ULPI Extended Register Address (ExtRegAddr): The 6-bit PHY extended register address.

RW 0x0
7:0 regdata

Contains the write data for register write. Read data for register read, valid when VStatus Done is Set.

 RW 0x0