devrd

Module Instance Base Address Register Address
qspiregs 0xFF705000 0xFF705004

Offset: 0x4

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

dummyrdclks

RW 0x0

Reserved

enmodebits

RW 0x0

Reserved

datawidth

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

addrwidth

RW 0x0

Reserved

instwidth

RW 0x0

rdopcode

RW 0x3

devrd Fields

Bit Name Description Access Reset
28:24 dummyrdclks

Number of dummy clock cycles required by device for read instruction.

 RW 0x0
20 enmodebits

If this bit is set, the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes.

Value Description
0x0 No Order
0x1 Mode Bits follow address bytes
RW 0x0
17:16 datawidth

Sets read data transfer width (1, 2, or 4 bits).

Value Description
0x0 Read data transferred on DQ0. Supported by all SPI flash devices
0x1 Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
0x2 Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.
RW 0x0
13:12 addrwidth

Sets read address transfer width (1, 2, or 4 bits).

Value Description
0x0 Read address transferred on DQ0. Supported by all SPI flash devices
0x1 Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
0x2 Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.
RW 0x0
9:8 instwidth

Sets instruction transfer width (1, 2, or 4 bits). Applies to all instructions sent to SPI flash device (not just read instructions).

Value Description
0x0 Instruction transferred on DQ0. Supported by all SPI flash devices.
0x1 Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
0x2 Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.
RW 0x0
7:0 rdopcode

Read Opcode to use when not in XIP mode

Value Description
0x3 Read Opcode in Non-XIP mode
0xb Fast Read in Non-XIP mode
RW 0x3