cfg

This is a STATUS read-only bit. Note this is a retimed signal, so there will be some inherent delay on the generation of this status signal.

SPI baud rate = ref_clk / (baud_rate_divisor)

If XIP is enabled, then setting to disabled will cause the controller to exit XIP mode on the next READ instruction. If XIP is disabled, then setting enable will operate the device in XIP mode immediately. Use this register when the external device wakes up in XIP mode (as per the contents of its non- volatile configuration register). The controller will assume the next READ instruction will be passed to the device as an XIP instruction, and therefore will not require the READ opcode to be transferred. Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only after the next READ instruction is executed. Software therefore should ensure that at least one READ instruction is requested after resetting this bit in order to be sure that XIP mode is exited.

If XIP is enabled, then setting to disabled will cause the controller to exit XIP mode on the next READ instruction. If XIP is disabled, then setting to enabled will inform the controller that the device is ready to enter XIP on the next READ instruction. The controller will therefore send the appropriate command sequence, including mode bits to cause the device to enter XIP mode. Use this register after the controller has ensured the FLASH device has been configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only AFTER the next READ instruction is executed. Software should therefore ensure that at least one READ instruction is requested after resetting this bit before it can be sure XIP mode in the device is exited.

(Direct Access Mode Only) When enabled, the incoming AHB address will be adapted and sent to the FLASH device as (address + N), where N is the value stored in the remap address register.

Allows DMA handshaking mode. When enabled the QSPI will trigger DMA transfer requests via the DMA peripheral interface.

This bit controls the write protect pin of the flash devices. The signal qspi_mo2_wpn needs to be resynchronized to the generated memory clock as necessary.

Peripheral chip select line output decode type. As per perseldec, if perseldec = 0, the decode is select 1 of 4 decoding on signals, qspi_n_ss_out[3:0], The asserted decode line goes to 0. If perseldec = 1, the signals qspi_n_ss_out[3:0] require an external 4 to 16 decoder.

Select between '1 of 4 selects' or 'external 4-to-16 decode'. The qspi_n_ss_out[3:0] output signals are controlled.

This bit can select the Direct Access Controller/Indirect Access Controller or legacy mode.If legacy mode is selected, any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid AHB read will pop the internal RX-FIFO, retrieving data that was forwarded by the external FLASH device on the SPI lines, byte transfers of 4, 2 or 1 are permitted and controlled via the HSIZE input.

If disabled, the Direct Access Controller becomes inactive once the current transfer of the data word (FF_W) is complete. When the Direct Access Controller and Indirect Access Controller are both disabled, all AHB requests are completed with an error response.

Selects whether the clock is in an active or inactive phase outside the SPI word.

Controls spiclk modes of operation.

If this bit is clear, the QSPI finishes the current transfer of the data word (FF_W) and stops sending. When this bit is set to 1, the QSPI is enabled. If the QSPI is enabled and qspi_n_mo_en=1, then the QSPI is able to initiate transfers on the bus. If the QSPI is enabled and qspi_n_mo_en = 0, all output enables are inactive and all pins are set to input mode.