FPGA2HPS Register Descriptions Registers associated with the FPGA2HPS AXI Bridge slave interface. This slave is used by the FPGA2HPS AXI Bridge to access slaves attached to the L3/L4 Interconnect. Offset: 0x4000 wr_tidemark Controls the release of the transaction in the write data FIFO. read_qos QoS (Quality of Service) value for the read channel. write_qos QoS (Quality of Service) value for the write channel. fn_mod Sets the block issuing capability to multiple or single outstanding transactions. Related reference DAP Register Descriptions MPU Register Descriptions SDMMC Register Descriptions DMA Register Descriptions ETR Register Descriptions EMAC0 Register Descriptions EMAC1 Register Descriptions USB0 Register Descriptions NAND Register Descriptions USB1 Register Descriptions