fpgamgrdata

Controls security settings for FPGA Manager Data peripheral.
Module Instance Base Address Register Address
l3regs 0xFF800000 0xFF80008C

Offset: 0x8C

Access: WO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

s

WO 0x0

fpgamgrdata Fields

Bit Name Description Access Reset
0 s

Controls whether secure or non-secure masters can access the FPGA Manager Data slave.

Value Description
0x0 The slave can only be accessed by a secure master.
0x1 The slave can only be accessed by a secure or non-secure masters.
WO 0x0