MIXED1IO17

This register is used to control the peripherals connected to qspi_io2 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance Base Address Register Address
sysmgr 0xFFD08000 0xFFD08544

Offset: 0x544

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

sel

RW 0x0

MIXED1IO17 Fields

Bit Name Description Access Reset
1:0 sel
Select peripheral signals connected qspi_io2.
Value Description
0x0 Pin is connected to GPIO/LoanIO number 31.
0x1 Pin is connected to Peripheral signal USB1.DIR.
0x2 Pin is connected to Peripheral signal not applicable.
0x3 Pin is connected to Peripheral signal QSPI.IO2.
RW 0x0