wddbg

Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These control registers are used to drive the pause input signal of the L4 watchdogs. Note that the watchdogs built into the MPU automatically are paused when their associated CPU enters debug mode. Only reset by a cold reset.
Module Instance Base Address Register Address
sysmgr 0xFFD08000 0xFFD08010

Offset: 0x10

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mode_1

RW 0x3

mode_0

RW 0x3

wddbg Fields

Bit Name Description Access Reset
3:2 mode_1

Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.

Value Description
0x0 Continue normal operation ignoring debug mode of CPUs
0x1 Pause normal operation only if CPU0 is in debug mode
0x2 Pause normal operation only if CPU1 is in debug mode
0x3 Pause normal operation if CPU0 or CPU1 is in debug mode
RW 0x3
1:0 mode_0

Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.

Value Description
0x0 Continue normal operation ignoring debug mode of CPUs
0x1 Pause normal operation only if CPU0 is in debug mode
0x2 Pause normal operation only if CPU1 is in debug mode
0x3 Pause normal operation if CPU0 or CPU1 is in debug mode
RW 0x3