gpio_ext_porta

Reading this register reads the values of the GPIO inputs.

Module Instance	Base Address	Register Address
`fpgamgrregs`	`0xFF706000`	`0xFF706850`

Offset: 0x850

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`				`fpo` `RO 0x0`	`cdp` `RO 0x0`	`nsp` `RO 0x0`	`ncp` `RO 0x0`	`prd` `RO 0x0`	`pre` `RO 0x0`	`prr` `RO 0x0`	`ccd` `RO 0x0`	`crc` `RO 0x0`	`id` `RO 0x0`	`cd` `RO 0x0`	`ns` `RO 0x0`

gpio_ext_porta Fields

Bit	Name	Description	Access	Reset
11	`fpo`	Reading this provides the value of FPGA_POWER_ON	`RO`	`0x0`
10	`cdp`	Reading this provides the value of CONF_DONE Pin	`RO`	`0x0`
9	`nsp`	Reading this provides the value of nSTATUS Pin	`RO`	`0x0`
8	`ncp`	Reading this provides the value of nCONFIG Pin	`RO`	`0x0`
7	`prd`	Reading this provides the value of PR_DONE	`RO`	`0x0`
6	`pre`	Reading this provides the value of PR_ERROR	`RO`	`0x0`
5	`prr`	Reading this provides the value of PR_READY	`RO`	`0x0`
4	`ccd`	Reading this provides the value of CVP_CONF_DONE	`RO`	`0x0`
3	`crc`	Reading this provides the value of CRC_ERROR	`RO`	`0x0`
2	`id`	Reading this provides the value of INIT_DONE	`RO`	`0x0`
1	`cd`	Reading this provides the value of CONF_DONE	`RO`	`0x0`
0	`ns`	Reading this provides the value of nSTATUS	`RO`	`0x0`