gpio_inttype_level

The interrupt level register defines the type of interrupt (edge or level) for each GPIO input.
Module Instance Base Address Register Address
fpgamgrregs 0xFF706000 0xFF706838

Offset: 0x838

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

fpo

RW 0x0

cdp

RW 0x0

nsp

RW 0x0

ncp

RW 0x0

prd

RW 0x0

pre

RW 0x0

prr

RW 0x0

ccd

RW 0x0

crc

RW 0x0

id

RW 0x0

cd

RW 0x0

ns

RW 0x0

gpio_inttype_level Fields

Bit Name Description Access Reset
11 fpo

Controls whether the level of FPGA_POWER_ON or an edge on FPGA_POWER_ON generates an interrupt.

Value Description
0x0 Level-sensitive
0x1 Edge-sensitive
RW 0x0
10 cdp

Controls whether the level of CONF_DONE Pin or an edge on CONF_DONE Pin generates an interrupt.

Value Description
0x0 Level-sensitive
0x1 Edge-sensitive
RW 0x0
9 nsp

Controls whether the level of nSTATUS Pin or an edge on nSTATUS Pin generates an interrupt.

Value Description
0x0 Level-sensitive
0x1 Edge-sensitive
RW 0x0
8 ncp

Controls whether the level of nCONFIG Pin or an edge on nCONFIG Pin generates an interrupt.

Value Description
0x0 Level-sensitive
0x1 Edge-sensitive
RW 0x0
7 prd

Controls whether the level of PR_DONE or an edge on PR_DONE generates an interrupt.

Value Description
0x0 Level-sensitive
0x1 Edge-sensitive
RW 0x0
6 pre

Controls whether the level of PR_ERROR or an edge on PR_ERROR generates an interrupt.

Value Description
0x0 Level-sensitive
0x1 Edge-sensitive
RW 0x0
5 prr

Controls whether the level of PR_READY or an edge on PR_READY generates an interrupt.

Value Description
0x0 Level-sensitive
0x1 Edge-sensitive
RW 0x0
4 ccd

Controls whether the level of CVP_CONF_DONE or an edge on CVP_CONF_DONE generates an interrupt.

Value Description
0x0 Level-sensitive
0x1 Edge-sensitive
RW 0x0
3 crc

Controls whether the level of CRC_ERROR or an edge on CRC_ERROR generates an interrupt.

Value Description
0x0 Level-sensitive
0x1 Edge-sensitive
RW 0x0
2 id

Controls whether the level of INIT_DONE or an edge on INIT_DONE generates an interrupt.

Value Description
0x0 Level-sensitive
0x1 Edge-sensitive
RW 0x0
1 cd

Controls whether the level of CONF_DONE or an edge on CONF_DONE generates an interrupt.

Value Description
0x0 Level-sensitive
0x1 Edge-sensitive
RW 0x0
0 ns

Controls whether the level of nSTATUS or an edge on nSTATUS generates an interrupt.

Value Description
0x0 Level-sensitive
0x1 Edge-sensitive
RW 0x0