ctrl

Allows HPS to control FPGA configuration. The NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields drive signals to the FPGA Control Block that are logically ORed into their respective pins. These signals are always driven independent of the value of EN. The polarity of the NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields is inverted relative to their associated pins. The MSEL (external pins), CDRATIO and CFGWDTH signals determine the mode of operation for Normal Configuration. For Partial Reconfiguration, CDRATIO is used to set the appropriate clock to data ratio, and CFGWDTH should always be set to 16-bit Passive Parallel. AXICFGEN is used to enable transfer of configuration data by enabling or disabling DCLK during data transfers.
Module Instance Base Address Register Address
fpgamgrregs 0xFF706000 0xFF706004

Offset: 0x4

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfgwdth

RW 0x1

axicfgen

RW 0x0

cdratio

RW 0x0

prreq

RW 0x0

confdonepull

RW 0x0

nstatuspull

RW 0x0

nconfigpull

RW 0x0

nce

RW 0x0

en

RW 0x0

ctrl Fields

Bit Name Description Access Reset
9 cfgwdth

This field determines the Configuration Passive Parallel data bus width when HPS configures the FPGA. Only 32-bit Passive Parallel or 16-bit Passive Parallel are supported. When HPS does Normal Configuration, configuration should use 32-bit Passive Parallel Mode. The external pins MSEL must be set appropriately for the configuration selected. For Partial Reconfiguration, 16-bit Passive Parallel must be used.

Value Description
0x0 16-bit Passive Parallel
0x1 32-bit Passive Parallel
RW 0x1
8 axicfgen

There are strict SW initialization steps for configuration, partial configuration and error cases. When SW is sending configuration files, this bit must be set before the file is transferred on the AXI bus. This bit enables the DCLK during the AXI configuration data transfers. Note, the AXI and configuration datapaths remain active irregardless of the state of this bit. Simply, if the AXI slave is enabled, the DCLK to the CB will be active. If disabled, the DCLK to the CB will not be active. So AXI transfers destined to the FPGA Manager when AXIEN is 0, will complete normally from the HPS perspective. This field only affects the FPGA if CTRL.EN is 1.

Value Description
0x0 Incoming AXI data transfers will be ignored. DCLK will not toggle during data transfer.
0x1 AXI data transfer to CB is active. DCLK will toggle during data transfer.
RW 0x0
7:6 cdratio

This field controls the Clock to Data Ratio (CDRATIO) for Normal Configuration and Partial Reconfiguration data transfer from the AXI Slave to the FPGA. For Normal Configuration, the value in this field must be set to be consistent to the implied CD ratio of the MSEL setting. For Partial Reconfiguration, the value in this field must be set to the same clock to data ratio in the options bits in the Normal Configuration file.

Value Description
0x0 CDRATIO of 1
0x1 CDRATIO of 2
0x2 CDRATIO of 4
0x3 CDRATIO of 8
RW 0x0
5 prreq

This field is used to assert PR_REQUEST to request partial reconfiguration while the FPGA is in User Mode. This field only affects the FPGA if CTRL.EN is 1.

Value Description
0x0 De-assert PR_REQUEST (driven to 0).
0x1 Assert PR_REQUEST (driven to 1).
RW 0x0
4 confdonepull

Pulls down CONF_DONE input to the CB

Value Description
0x0 Don't pull-down CONF_DONE input to the CB.
0x1 Pull-down CONF_DONE input to the CB.
RW 0x0
3 nstatuspull

Pulls down nSTATUS input to the CB

Value Description
0x0 Don't pull-down nSTATUS input to the CB.
0x1 Pull-down nSTATUS input to the CB.
RW 0x0
2 nconfigpull

The nCONFIG input is used to put the FPGA into its reset phase. If the FPGA was configured, its operation stops and it will have to be configured again to start operation.

Value Description
0x0 Don't pull-down nCONFIG input to the CB.
0x1 Pull-down nCONFIG input to the CB. This puts the FPGA in reset phase and restarts configuration.
RW 0x0
1 nce

This field drives the active-low Chip Enable (nCE) signal to the CB. It should be set to 0 (configuration enabled) before CTRL.EN is set. This field only effects the FPGA if CTRL.EN is 1.

Value Description
0x0 Configuration is enabled. The nCE to the CB is driven to 0.
0x1 Configuration is disabled. The nCE to the CB is driven to 1.
RW 0x0
0 en

Controls whether the FPGA configuration pins or HPS FPGA Manager drive configuration inputs to the CB.

Value Description
0x0 FPGA configuration pins drive configuration inputs to the CB. Used when FPGA is configured by means other than the HPS.
0x1 FPGA Manager drives configuration inputs to the CB. Used when HPS configures the FPGA.
RW 0x0