data

Used to send configuration image to FPGA. The DATA register accepts 4 bytes of the configuration image on each write. The configuration image byte-stream is converted into a 4-byte word with little-endian ordering. If the configuration image is not an integer multiple of 4 bytes, software should pad the configuration image with extra zero bytes to make it an integer multiple of 4 bytes. The FPGA Manager converts the DATA to 16 bits wide when writing CB.DATA for partial reconfiguration. The FPGA Manager waits to transmit the data to the CB until the FPGA is able to receive it. For a full configuration, the FPGA Manager waits until the FPGA exits the Reset Phase and enters the Configuration Phase. For a partial reconfiguration, the FPGA Manager waits until the CB.PR_READY signal indicates that the FPGA is ready.

Module Instance	Base Address	Register Address
`fpgamgrdata`	`0xFFB90000`	`0xFFB90000`

Offset: 0x0

Access: RW

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`value` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`value` `RW 0x0`

data Fields

Bit	Name	Description	Access	Reset
31:0	`value`	Accepts configuration image to be sent to CB when the HPS configures the FPGA. Software normally just writes this register. If software reads this register, it returns the value 0 and replies with an AXI SLVERR error.	`RW`	`0x0`