miscmodrst

The MISCMODRST register is used by software to trigger module resets (individual module reset signals). Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up to software to ensure module reset signals are asserted for the appropriate length of time and are de-asserted in the correct order. It is also up to software to not assert a module reset signal that would prevent software from de-asserting the module reset signal. For example, software should not assert the module reset to the CPU executing the software. Software writes a bit to 1 to assert the module reset signal and to 0 to de-assert the module reset signal. All fields are only reset by a cold reset
Module Instance Base Address Register Address
rstmgr 0xFFD05000 0xFFD05020

Offset: 0x20

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

sdrcold

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

tapcold

RW 0x0

dbg

RW 0x0

sysdbg

RW 0x0

frzctrlcold

RW 0x0

scanmgr

RW 0x0

clkmgrcold

RW 0x0

timestampcold

RW 0x0

nrstpin

RW 0x0

s2fcold

RW 0x0

s2f

RW 0x0

acpidmap

RW 0x0

fpgamgr

RW 0x0

sysmgrcold

RW 0x0

sysmgr

RW 0x0

ocram

RW 0x0

rom

RW 0x0

miscmodrst Fields

Bit Name Description Access Reset
16 sdrcold

Resets logic in SDRAM Controller Subsystem affected only by a cold reset.

 RW 0x0
15 tapcold

Resets portion of DAP JTAG TAP controller no reset by a debug probe reset (i.e. nTRST pin). Cold reset only.

 RW 0x0
14 dbg

Resets logic located only in the debug domain.

 RW 0x0
13 sysdbg

Resets logic that spans the system and debug domains.

 RW 0x0
12 frzctrlcold

Resets Freeze Controller in System Manager (cold reset only)

 RW 0x0
11 scanmgr

Resets Scan Manager

 RW 0x0
10 clkmgrcold

Resets Clock Manager (cold reset only)

 RW 0x0
9 timestampcold

Resets debug timestamp to 0 (cold reset only)

 RW 0x0
8 nrstpin

Pulls nRST pin low

 RW 0x0
7 s2fcold

Resets logic in FPGA core that is only reset by a cold reset (ignores warm reset) (h2f_cold_rst_n = 1)

 RW 0x0
6 s2f

Resets logic in FPGA core that doesn't differentiate between HPS cold and warm resets (h2f_rst_n = 1)

 RW 0x0
5 acpidmap

Resets ACP ID Mapper

 RW 0x0
4 fpgamgr

Resets FPGA Manager

 RW 0x0
3 sysmgrcold

Resets logic in System Manager that is only reset by a cold reset (ignores warm reset)

 RW 0x0
2 sysmgr

Resets logic in System Manager that doesn't differentiate between cold and warm resets

 RW 0x0
1 ocram

Resets On-chip RAM

 RW 0x0
0 rom

Resets Boot ROM

 RW 0x0