ctrl

The CTRL register is used by software to control reset behavior.It includes fields for software to initiate the cold and warm reset, enable hardware handshake with other modules before warm reset, and perform software handshake. The software handshake sequence must match the hardware sequence. Software mustde-assert the handshake request after asserting warm reset and before de-assert the warm reset. Fields are only reset by a cold reset.
Module Instance Base Address Register Address
rstmgr 0xFFD05000 0xFFD05004

Offset: 0x4

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

etrstallwarmrst

RW 0x0

etrstallack

RO 0x0

etrstallreq

RW 0x0

etrstallen

RW 0x1

Reserved

fpgahsack

RO 0x0

fpgahsreq

RW 0x0

fpgahsen

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

scanmgrhsack

RO 0x0

scanmgrhsreq

RW 0x0

scanmgrhsen

RW 0x0

Reserved

fpgamgrhsack

RO 0x0

fpgamgrhsreq

RW 0x0

fpgamgrhsen

RW 0x0

Reserved

sdrselfreqack

RO 0x0

sdrselfrefreq

RW 0x0

sdrselfrefen

RW 0x0

Reserved

swwarmrstreq

RW 0x0

swcoldrstreq

RW 0x0

ctrl Fields

Bit Name Description Access Reset
23 etrstallwarmrst

If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to indicate that the stall of the ETR AXI master is pending. Hardware leaves the ETR stalled until software clears this field by writing it with 1. Software must only clear this field when it is ready to have the ETR AXI master start making AXI requests to write trace data.

RW 0x0
22 etrstallack

This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ field. A 1 indicates that the ETR has stalled its AXI master

RO 0x0
21 etrstallreq

Software writes this field 1 to request to the ETR that it stalls its AXI master to the L3 Interconnect. Software waits for the ETRSTALLACK to be 1 and then writes this field to 0. Note that it is possible for the ETR to never assert ETRSTALLACK so software should timeout if ETRSTALLACK is never asserted.

RW 0x0
20 etrstallen

This field controls whether the ETR is requested to idle its AXI master interface (i.e. finish outstanding transactions and not initiate any more) to the L3 Interconnect before a warm or debug reset. If set to 1, the Reset Manager makes a request to the ETR to stall its AXI master and waits for it to finish any outstanding AXI transactions before a warm reset of the L3 Interconnect or a debug reset of the ETR. This stalling is required because the debug logic (including the ETR) is reset on a debug reset and the ETR AXI master is connected to the L3 Interconnect which is reset on a warm reset and these resets can happen independently.

RW 0x1
18 fpgahsack

This is the acknowlege (high active) that the FPGA handshake acknowledge has been received by Reset Manager.

RO 0x0
17 fpgahsreq

Software writes this field 1 to initiate handshake request to FPGA . Software waits for the FPGAHSACK to be active and then writes this field to 0. Note that it is possible for the FPGA to never assert FPGAHSACK so software should timeout in this case.

RW 0x0
16 fpgahsen

This field controls whether to perform handshake with FPGA before asserting warm reset. If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm reset signals. However if FPGA is already in warm reset state, the handshake is not performed. If set to 0, the handshake is not performed

RW 0x0
14 scanmgrhsack

This is the acknowlege (high active) that the SCAN manager has successfully idled its output clocks.

RO 0x0
13 scanmgrhsreq

Software writes this field 1 to request to the SCAN manager to idle its output clocks. Software waits for the SCANMGRHSACK to be 1 and then writes this field to 0. Note that it is possible for the Scan Manager to never assert SCANMGRHSACK (e.g. its input clock is disabled) so software should timeout in this case.

RW 0x0
12 scanmgrhsen

Enables a handshake between the Reset Manager and Scan Manager before a warm reset. The handshake is used to warn the Scan Manager that a warm reset it coming so it can prepare for it. When the Scan Manager receives a warm reset handshake, the Scan Manager drives its output clocks to a quiescent state to avoid glitches. If set to 1, the Reset Manager makes a request to the Scan Managerbefore asserting warm reset signals. However if the Scan Manager is already in warm reset, the handshake is skipped. If set to 0, the handshake is skipped.

RW 0x0
10 fpgamgrhsack

This is the acknowlege (high active) that the FPGA manager has successfully idled its output clock.

RO 0x0
9 fpgamgrhsreq

Software writes this field 1 to request to the FPGA Manager to idle its output clock. Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0. Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so software should timeout in this case.

RW 0x0
8 fpgamgrhsen

Enables a handshake between the Reset Manager and FPGA Manager before a warm reset. The handshake is used to warn the FPGA Manager that a warm reset it coming so it can prepare for it. When the FPGA Manager receives a warm reset handshake, the FPGA Manager drives its output clock to a quiescent state to avoid glitches. If set to 1, the Manager makes a request to the FPGA Managerbefore asserting warm reset signals. However if the FPGA Manager is already in warm reset, the handshake is skipped. If set to 0, the handshake is skipped.

RW 0x0
6 sdrselfreqack

This is the acknowlege for a SDRAM self-refresh mode request initiated by the SDRSELFREFREQ field. A 1 indicates that the SDRAM Controller Subsystem has put the SDRAM devices into self-refresh mode.

RO 0x0
5 sdrselfrefreq

Software writes this field 1 to request to the SDRAM Controller Subsystem that it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM contents across a software warm reset. Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0. Note that it is possible for the SDRAM Controller Subsystem to never assert SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted.

RW 0x0
4 sdrselfrefen

This field controls whether the contents of SDRAM devices survive a hardware sequenced warm reset. If set to 1, the Reset Manager makes a request to the SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode before asserting warm reset signals. However, if SDRAM is already in warm reset, Handshake with SDRAM is not performed.

RW 0x0
1 swwarmrstreq

This is a one-shot bit written by software to 1 to trigger a hardware sequenced warm reset. It always reads the value 0.

RW 0x0
0 swcoldrstreq

This is a one-shot bit written by software to 1 to trigger a cold reset. It always reads the value 0.

RW 0x0