stat

The STAT register contains bits that indicate the reset source or a timeout event. For reset sources, a field is 1 if its associated reset requester caused the reset. For timeout events, a field is 1 if its associated timeout occured as part of a hardware sequenced warm/debug reset. Software clears bits by writing them with a value of 1. Writes to bits with a value of 0 are ignored. After a cold reset is complete, all bits are reset to their reset value except for the bit(s) that indicate the source of the cold reset. If multiple cold reset requests overlap with each other, the source de-asserts the request last will be logged. The other reset request source(s) de-assert the request in the same cycle will also be logged, the rest of the fields are reset to default value of 0. After a warm reset is complete, the bit(s) that indicate the source of the warm reset are set to 1. A warm reset doesn't clear any of the bits in the STAT register; these bits must be cleared by software writing the STAT register. During the boot process, the Boot ROM copies the STAT register value into memory before clearing it. After booting, you can read the value of the reset status register at memory address (r0 + 0x0038).
Module Instance Base Address Register Address
rstmgr 0xFFD05000 0xFFD05000

Offset: 0x0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

etrstalltimeout

RW 0x0

fpgahstimeout

RW 0x0

scanhstimeout

RW 0x0

fpgamgrhstimeout

RW 0x0

sdrselfreftimeout

RW 0x0

Reserved

cdbgreqrst

RW 0x0

fpgadbgrst

RW 0x0

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

l4wd1rst

RW 0x0

l4wd0rst

RW 0x0

mpuwd1rst

RW 0x0

mpuwd0rst

RW 0x0

Reserved

swwarmrst

RW 0x0

fpgawarmrst

RW 0x0

nrstpinrst

RW 0x0

Reserved

swcoldrst

RW 0x0

configiocoldrst

RW 0x0

fpgacoldrst

RW 0x0

nporpinrst

RW 0x0

porvoltrst

RW 0x0

stat Fields

Bit Name Description Access Reset
28 etrstalltimeout

A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to stall its AXI master port before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.

 RW 0x0
27 fpgahstimeout

A 1 indicates that Reset Manager's handshake request to FPGA before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.

 RW 0x0
26 scanhstimeout

A 1 indicates that Reset Manager's request to the SCAN manager to stop driving JTAG clock to FPGA CB before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.

 RW 0x0
25 fpgamgrhstimeout

A 1 indicates that Reset Manager's request to the FPGA manager to stop driving configuration clock to FPGA CB before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.

 RW 0x0
24 sdrselfreftimeout

A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.

 RW 0x0
19 cdbgreqrst

DAP triggered debug reset

 RW 0x0
18 fpgadbgrst

FPGA triggered debug reset (f2h_dbg_rst_req_n = 1)

 RW 0x0
15 l4wd1rst

L4 Watchdog 1 triggered a hardware sequenced warm reset

 RW 0x0
14 l4wd0rst

L4 Watchdog 0 triggered a hardware sequenced warm reset

 RW 0x0
13 mpuwd1rst

MPU Watchdog 1 triggered a hardware sequenced warm reset

 RW 0x0
12 mpuwd0rst

MPU Watchdog 0 triggered a hardware sequenced warm reset

 RW 0x0
10 swwarmrst

Software wrote CTRL.SWWARMRSTREQ to 1 and triggered a hardware sequenced warm reset

 RW 0x0
9 fpgawarmrst

FPGA core triggered a hardware sequenced warm reset (f2h_warm_rst_req_n = 1)

 RW 0x0
8 nrstpinrst

nRST pin triggered a hardware sequenced warm reset

 RW 0x0
4 swcoldrst

Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset

 RW 0x0
3 configiocoldrst

FPGA entered CONFIG_IO mode and a triggered a cold reset

 RW 0x0
2 fpgacoldrst

FPGA core triggered a cold reset (f2h_cold_rst_req_n = 1)

 RW 0x0
1 nporpinrst

nPOR pin triggered a cold reset (por_pin_req = 1)

 RW 0x0
0 porvoltrst

Built-in POR voltage detector triggered a cold reset (por_voltage_req = 1)

 RW 0x0