dramtiming3

This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor.

Module Instance	Base Address	Register Address
`sdr`	`0xFFC20000`	`0xFFC2500C`

Offset: 0x500C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`									`tccd` `RW 0x0`				`tmrd` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`tmrd` `RW 0x0`	`trc` `RW 0x0`						`tras` `RW 0x0`					`trtp` `RW 0x0`

dramtiming3 Fields

Bit	Name	Description	Access	Reset
22:19	`tccd`	The CAS to CAS delay time.	`RW`	`0x0`
18:15	`tmrd`	Mode register timing parameter.	`RW`	`0x0`
14:9	`trc`	The activate to activate timing parameter.	`RW`	`0x0`
8:4	`tras`	The activate to precharge timing parameter.	`RW`	`0x0`
3:0	`trtp`	The read to precharge timing parameter.	`RW`	`0x0`